1. Field of the Invention
The present invention relates to a timing recovery circuit, and particularly to a timing recovery circuit and a method thereof which avoids a steady estimation error of the frequency and phase resulting from rounding-off imprecision of digital processing.
2. Description of the Prior Art
There are signals transmitted from a transmission end to a receiving end in digital processing or communication systems. Basically, the signals received on the receiving end must be synchronized with those from the transmission end to eliminate the frequency and phase errors generated in the transmission channel. Further, there is always a difference between the sampling rates of the digital signals on the transmission and receiving ends since the circuitries on these two ends are independent of each other. Therefore, there must be a timing recovery means working on the sampling frequency and phase for signal synchronization.
FIG. 1 is a diagram showing a conventional timing recovery circuit 1, which includes an analog-to-digital converter (ADC) 11, an interpolator 12, a phase error detector 13, an over-sampling ratio (OSR) adjustment circuit 14 and a MU calculation circuit 15. The analog-to-digital converter 11 samples a received analog signal r(t) at a sampling rate provided by a clock signal CLK. The digital signal output from the analog-to-digital converter 11 is usually asynchronized since there is a difference between the symbol rate of the signal r(t) and that of the analog-to-digital converter 11. The interpolator 12 processes the signal output from the ADC 11 for signal synchronization so that interpolating samples can be derived and inserted into the asynchronous signal. Basically, timing of the interpolating sample insertions is determined by a control value MU (μ). The synchronized signal output from the interpolator 12 is fed to the phase error detector 13 to detect and output a phase error PhaseErr. Initially, the OSR adjustment circuit 14 outputs an initial over-sampling ratio, which is a ratio of the sampling rate of the ADC 11 to the data rate. As the phase error PhaseErr is generated and output by the phase error detector 13, the OSR adjustment circuit 14 derives a new over-sampling ratio by the following equation:OSR(k)=OSR(k−1)+k2*PhaseErr,  (eq. 1)wherein k2 is a constant and k is the order. The MU calculation circuit 15 derives the control value MU by using the following equation:MU(k)=MU(k−1)+OSR(k)−1+PhaseErr*k1,  (eq. 2)wherein k1 is a constant.
Thus, the timing recovery circuit 1 generates an output signal with synchronized frequency and phase via the closed loop formed by the phase error detector 13, OSR adjustment circuit 14 and MU calculation circuit 15.
For the sake of cost, floating point numbers is not practically used for the phase error, OSR and control value MU. Instead, fixed point numbers are typically used, which obviously results in rounding-off imprecision.
FIG. 2 is a diagram showing phase error values that changes as a function of time when the floating point numbers are used. The OSR converges onwards a true OSR, and thus the average value of the phase error within any short time period is theoretically zero since the phase error is actually a white noise.
FIG. 3 is a diagram showing the phase error values changing as a function of time when the fixed point numbers are used. Since the phase error are wobbling alone the zero line, only the average value of the phase error within a relatively long time period approaches zero rather than within a short time period.
Accordingly, in the conventional timing recovery circuit, the phase error increases successively rather than decreases due to the rounding error, which indicates that a relatively long time period is required for reducing the phase error. Moreover, the phase of the synchronized signal swings around the correct one, which makes the OSR or sampling rate of the ADC swing in the same way.